This invention relates to a clock generator, particular to a clock generator generating a synchronous clock intermittently.
It is known that, in a logic circuit driven by the synchronous clock, a consumed current increases in proportion to the frequency of the clock. In a system using the logic circuit, it is a key issue to reduce current consumption. As a power saving method for a logic circuit driven by a synchronous clock, there is a technique that generates the synchronous clock to be supplied to the logic circuit intermittently according to a required processing speed.
Further, when a parallel processing is performed by a plurality of logic circuits, a required processing speed generally differs depending on processing. When a clock suitable for each processing speed is supplied to the plurality of logic circuits in an intermittent manner, the timing at the peak power of each logic circuit coincides thereby increasing the entire peak power. Therefore, a means of scattering the timing of each peak power is required.
A clock generator to achieve low power consumption suitable for a required processing speed is disclosed in Japanese Unexamined Patent Application Publication No. 07-129272 (Patent literature 1), for example. The clock generator is described hereinafter with reference to FIGS. 10 and 11. FIG. 10 is a block diagram to illustrate an overall configuration of the clock generator according to related art which is disclosed in Patent literature 1. FIG. 11 is a timing chart to illustrate a clock waveform of the clock generator according to the related art.
In FIG. 10, an oscillator 101 outputs a clock 104 with a constant frequency, like a crystal oscillator, for example. A clock rate control circuit 102 controls the clock 104 to generate an operating clock 105. A logic circuit 103 operates with the operating clock 105. The clock rate control circuit 102 generates the operating clock 105 as an intermittent clock and varies the number of clock pulses per unit time according to processing speed requirements.
The operating clock 105 is processed into a waveform 108 or a waveform 109 shown in FIG. 11, for example, by the clock rate control circuit 102. The waveform 108 is to obtain a processing speed of 100%, which is the same as a waveform 107 of the clock 104. The waveform 109 is to obtain a processing speed of 75%, in which a continuous period and an idle period of the clock are repeated at a ratio of 3:1. In FIG. 11, the waveform 109 involves repetition of the continuous period where the clock continues for the duration of six pulses and the idle period where the clock is suspended for the duration of two pulses.